1. Field of the Invention
This invention relates to a novel semiconductor package and a computer which uses it.
2. Prior Art Statement
Recent demands for faster and more compact computers based on semiconductor devices have spurred higher degrees of integration and larger semiconductor devices. They have also led to an increase in the number of terminal electrodes used for connecting semiconductor devices to the outside. In order to deal with ever greater numbers of terminals, the method of controlled collapse bonding (CCB) in which many electrodes are regularly arranged on one main surface of the semiconductor device has been used in packages of a structure in which electrodes on the semiconductor device are electrically connected to electrodes on a package substrate used for mounting the semiconductor device. Radiation of heat from such package substrates to which semiconductor devices are mounted by means of the CCB method is covered, as in Japanese Laid-Open Patent Publication (JP-A) 62-249429, by connecting a surface of the package on which electrodes of the semiconductor device are not formed to a cap substrate with solder or other thermally conductive material, but no attention is paid to wiring within the base substrate. Multi-layer base substrates normally include a conductive layer for signal transmission, a conductive layer for power supply, a conductive layer for connection to ground and conductive layers for many other systems. With such conventional package structures, the conductive layer for power supply within the substrate, like the conductive layer for signal transmission and conductive layer for connection to ground, is wired with fine lines of nearly uniform cross-sectional shape, each connected to terminals for connecting to the outside. In addition, for computers which are normally required to perform high-speed operations, in order to suppress voltage fluctuations due to instantaneous current during signal switching, capacitor devices have been built into the printed substrate onto which the package is mounted, or the package has been connected to a nearby capacitor device, or as seen in Japanese Laid-Open Patent Publication (JP-A) No. 62-169461, a structure in which capacitor devices are formed on part of the package has been employed.
Furthermore, with respect to higher densities and higher degrees of integration, the presently main-stream DIP package is being replaced by packages with structures suited to connection of many terminals, such as flat packages in which the terminals for connecting to the outside are arranged along the four edges of the package substrate, and PGA-type packages in which terminals for connecting to the outside are arranged on a single face of the package substrate.
An example of flat packages is a 200-pin class package disclosed in "Components and Packaging for the FACOM M-780" FUJITSU 37.2. pp. 116-123.
On the other hand, while high speed has not posed any particular problem up until now, conventional packages are becoming unable to satisfy performance requirements. Current flowing through a package can be broadly divided into two types, each requiring different properties. The first is signal current which is required to have as short of rise and fall times as possible. This requirement, expressed as conditions for the transmission circuits, means that inductance and capacitance are to be reduced to as low of level as possible. The other type of current flowing through the package is the power-source current. Fluctuations in the power-source voltage due to load fluctuations are required to be kept as low as possible. To achieve this end, inductance in the transmission circuit for the power-source current should be reduced but capacitance should be increased. Conventional packages cannot assure sufficient capacitance, so the function of stabilizing voltage was not required of the package so only reduction of inductance is aimed for. As a means of realizing this, the transmission path for the power-source current is made shorter than that of the signal current, specifically by bringing the power-source pin close to the semiconductor device (or near the center of the four edges). Yet this method, while reducing the inductance of the power-source line, also reduces the capacitance at the same time. Moreover, this involves the problem of a proportionate increase in the inductance and capacitance of the signal lines.
No conventional packages have structures which allow the different requirements of the power-source lines and signal lines to be satisfied simultaneously.
When a capacitor device is externally attached near the package, the length of wiring from the semiconductor device to the capacitor, so the power-source voltage fluctuations cannot be sufficiently suppressed. Since the wiring lines in the conductive layers for power supply and connection to ground are thin, they are susceptible to fluctuations in power-source voltage from the outside, becoming one cause of malfunctions. Furthermore, the conductive layer for signal transmission extends into the periphery within the package substrate, and the terminals are positioned among the terminals of conductive layers for power supply and connection to ground. For this reason, the length of wiring which passes through a ceramic substrate of a high dielectric constant is long so the signal transmission lag time becomes large. Also, in a structure as seen in Japanese Laid-Open Patent Publication (JP-A) No. 62-169461, in which a capacitor device is formed in part of the package, since a capacitor is formed on the side on which the heat generated by the semiconductor device is dissipated, effective thermal resistance within the package increases so that heat radiation would be insufficient if mounted with one of the semiconductor devices which have in recent years become larger, more highly integrated and generate more heat.